In the fabrication of integrated devices and circuits, photolithography or optical lithography is used to selectively remove parts of a thin film layer or a part of the substrate. The process conventionally uses light to transfer a pattern from a photomask to a light-sensitive chemical (photoresist, or simply “resist”) on the substrate (or other layer). A series of treatments then engraves the exposure pattern into the materials underlying the photoresist. In a complex IC, a wafer will go through the photolithographic cycle up to 50 times.
In conventional photolithography the mask patterns encode and image to resemble the intended patterns (the “design intent”) to be created on the underlying wafer layer. An exposure system typically produces an image on the wafer using the mask. An illumination system shines light through the mask blocking it in some areas and letting it pass in others. Most VLSI lithography uses a projection system in which a mask (also called a “reticle”) to create patterns for a single or small number of chips or dies. The projection system (also called a “scanner” or “stepper”) projects the mask image onto the wafer many times to create the complete wafer pattern. The pattern on the mask is typically projected and reduced by four times on the wafer surface.
Current state-of-the-art photolithography tools use deep ultraviolet (DUV) light with wavelengths of 248 and 193 nm for feature sizes or critical dimensions (CDs) down to about 32 nm. The DUV light is typically produced by excimer lasers, with Krypton fluoride producing a 248 nm spectral line and argon fluoride a 193 nm line.
Double exposure techniques use a sequence of two separate exposures of the same photoresist layer using two different photomasks. This technique has been proposed for patterns in the same layer that look very different or have incompatible densities or pitches. In one case, the two exposures may each consist of lines that are oriented in one or the other of two usually perpendicular directions. In another case using alternating phase-shifting mask (alt-PSM), two exposures are needed to resolve conflicts in phase assignments of the phase shifters. See, e.g., U.S. Pat. No. 5,858,580. In still another case, two exposures are used to produce images corresponding to the real and imaginary parts of a complex-valued mask transmittance function (See for example, Y. C. Pati and T. Kailath, “Phase-shifting masks for microlithography: automated design and mask requirements,” J. Opt. Soc. Am. A, vol. 11, no. 9, pp. 2438-2452, September 1994). Although double exposure as a particular technique enhances the resolution of resist image, the obtainable CD and especially pitch of patterns are still fundamentally limited by optical diffraction.
In order to further enhance feature density while avoiding infrastructure changes, various multiple patterning technologies have been proposed to fraction the pitch of patterns as limited by optical imaging (thus multiply the pattern density). Multiple patterning offers the advantage of scanner/stepper re-use for more than one technology generation, by allowing pitch to shrink. In a typical two-exposure double patterning process using either positive or negative photoresists or hard masks, a first exposure defines a first set of patterns in a first photoresist film, which are transferred onto a film of hard mask by an etching process, then the first photoresist film is removed and a second photoresist film is coated; Subsequently, a second exposure defines a second set of patterns in the second photoresist film, which are transferred onto the film of hard mask by an etching process, then the second photoresist film is removed; Finally, another etching process transfers the patterns in the hard mask onto the underlying device layer.
Another technique of double patterning has been proposed using “spacer masks”, where only one exposure is used to build “posts”, and then a spacer mask material is deposited to surround the posts. Spacers are formed by deposition or reaction of the film on the posts. Then an etching or chemical mechanical polishing (CMP) step may be employed to remove the spacer material on the top surfaces of the posts, leaving only the material on the sidewalls. By removing the original post patterns, only the spacers are left. Since there are two spacers for each line of post, the line density is effectively doubled. This “spacer mask” technique saves one exposure, but it lacks design flexibility, due to the fact that spacer lines must be generated in pairs. Other issues with the spacer mask approach include: (1) whether the spacers will stay in place after the post material is removed, (2) whether the spacer profile is acceptable, and (3) whether the underlying material is etched when removing the post material. Pattern transfer is complicated by the situation where removal of the post material also removes some of the underlying material, which results in uneven topography between the two sides of a spacer.
Another double pattering technique has been referred to as a “heterogeneous mask” technique, wherein a first exposure and development of photoresist transfers patterns to an underlying hard mask layer. After the photoresist being removed, a second layer of photoresist is coated. This second layer undergoes a second exposure and development, forming patterns in between the features patterned in the hard mask layer. The surface pattern is therefore a combination of photoresist features and hard mask features. This pattern is then transferred into the final layer underneath, with the prospect of increasing the feature density. A concern with the use of the hetorogeneous mask approach is the large discrepancy in mechanical and chemical properties between the second photoresist (usually a polymer) pattern and the first hard mask (often an inorganic) pattern, resulting in additional sources of variations in CD uniformity and etching rate. For further details on various techniques of double patterning, see for example, W. Arnold, M. Dusa, and J. Finders, “Metrology challenges for double exposure and double patterning,” Proc. SPIE, vol. 6518, 651802, 2007; Y. Nagaoka and H. Watanabe, “PMJ 2007 Panel Discussion Overview: double exposure and double patterning for 32-nm half-pitch design node,” Proc. SPIE, vol. 6730, 673006, 2007; and J. Finders, M. Dusa, and S. Hsu, “Double patterning lithography: The bridge between low k1 ArF and EUV,” Microlithography World, vol. 17, no. 1, pp. 2, 4-6, 12, February, 2008.
The above techniques of double patterning may be extended to multi-patterning ones (also known as “intermediate pattern accumulation” techniques), which involve a sequence of multiple separate exposures and etchings of different patterns into the same layer of hard mask. For each exposure, a different photoresist coating may be used. When the sequence is completed, the pattern in the hard mask is a composite of the previously etched subpatterns as transferred from previous resist patterns generated by the multiple exposures and resist developments. By interleaving the subpatterns, the pattern density could theoretically be increased indefinitely beyond the Rayleigh limit of optical imaging, with an effective pitch being inversely proportional to the number of subpatterns.
The above described multiple patterning techniques have drawbacks and are associated with technical difficulties. Apart from the particular issues concerning each specific technique, a general problem is the stringent requirement of overlay among subpatterns, as the positioning of another subpattern relative to the existing subpattern(s) determines the spacing size. Substantially higher precision is required for lithography tool overlay, reticle-to-reticle overlay, and reticle-to-reticle CD and figure placement matching, etc. Overlay error induced pattern mismatches and CD nonuniformity may be significant sources of process variations that limit chip yield and performance.
The above described multiple patterning techniques face further general difficulties in the optical imaging process due to the smaller feature sizes of subpatterns, which reduce tolerances to exposure dose and focus variations, mask errors, and projection optics imperfections, hence result in smaller process windows. As an overly simplified example, a 100 nm process with a 10 nm tolerance may have to be tightened to a 5 nm tolerance before application to a 50 nm process using a double patterning strategy.
Still further, there is the general problem of pattern splitting conflict. Splitting a design between two or more complementary masks may be conveniently done only for highly repetitive patterns like those in random access memory or flash memory chips. Pattern splitting becomes substantially more difficult for logic chip patterns that are less regular. If a line needs to be split in the middle and stitched back together, seamless stitching can be challenging. Even with perfect overlays, a location having two line segments stitched together could hardly be as clean as a whole line being printed in one shot. Therefore, when a line needs to be split, the splitting location has to be carefully chosen to minimize the impact to device performance. Unfortunately, such pattern splitting considerations increases the complexity of chip design.
Accordingly, there is a need for a lithography technique to significantly decrease the minimum feature size, and increase the pattern density, without requiring major infrastructure changes, while avoiding the above-mentioned problems associated with known multiple patterning techniques. In particular, there is a need for a multi-exposure multi-patterning technique that relaxes the overlay requirements to lithography tools and photomasks, enlarges tolerances to optical imaging process variations, and does not incure the problem of pattern splitting conflict.